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1. Field of the Invention
This invention relates generally to automatic test equipment (ATE) for electronics, and, more particularly, to test equipment that includes circuitry for converting parallel data to serial bit streams for testing electronic devices.
2. Description of Related Art Including Information Disclosed Under 37 C.F.R. 1.97 and 1.98
Manufacturers of semiconductor devices commonly use testers, or automatic test equipment (ATE), to test whether devices meet their requirements. Devices that fail their tests can be discarded early in the manufacturing process, before additional costs are incurred. Devices with different levels of performance can be sorted into different categories, in response to test results, for sale at different prices.
As one of their many functions, testers generate stimulus signals for testing electronic devices. As shown in FIG. 1, data for generating stimulus signals are conventionally stored in a parallel memory 110. An address counter 112 addresses the memory 110 and increments upon each cycle of a memory clock (M-CLK). For applying parallel signals to a device under test (DUT), the memory 110 feeds data words to a bank of driver circuits (not shown). Each driver circuit buffers one bit of the memory and applies the buffered bit to a different node of the DUT. For generating serial data, the memory 110 feeds data to a serializer 114, which converts the parallel data to serial form. The serial data is then buffered by a driver circuit, which sends the buffered signal to a node of the DUT.
The serializer generally outputs serial data at a rate that equals the frequency of M-CLK times the word width of the memory 110. For example, if M-CLK runs at 100 MHz and the memory 110 stores data words that are 32-bits wide, the serializer outputs serial data at the rate of 32*100 MHz=3.2 GHz. The serializer""s use of word width as a multiplier of output frequency ensures that the serializer outputs serial data continuously, without overlaps or gaps, to keep pace precisely with incoming data from the memory 110.
A need commonly arises in automatic testing to loop on a particular test pattern or group of test patterns. Each test pattern is generally encoded within a contiguous block of memory. To loop on a test pattern, the address counter 112 is set to a xe2x80x9cbase address,xe2x80x9d i.e., the memory address at which the pattern begins, and is caused to increment through the memory. As the address counter increments, the tester outputs test signals that correspond to the data stored in the memory. After reaching the last address in the memory of the test pattern, the address counter is reset to the base address and the test pattern is repeated. Because the tester restores the address counter to the base address on the very next cycle of M-CLK after it has assumed the last address, the loop proceeds continuously, without interruption.
A problem arises, however, when the test pattern prescribes a serial bit stream that contains a number of bits that is not an integer multiple of the memory word width. Consider the example shown in FIG. 2. A serial bit stream is encoded within four 32-bit memory words: W0-W3. The last word, W3, is only partially filled with dataxe2x80x94it contains only 21 of a possible 32 bits. If the tester were to loop on this pattern, it would produce an 11-bit timing gap (32 bitsxe2x88x9221 bits) corresponding to the time between the end of the current iteration of the pattern and the beginning of the next iteration.
This interruption in the output waveform can detrimentally affect testing. For example, many devices for which serial testing is sought tend to behave predictably when driven by known test patterns, but can deviate from their predicted behavior when the test pattern changes. Maintaining the test pattern without interruption is thus critical to ensuring predictable behavior of the device under test.
What is needed is a way of eliminating timing gaps that arise when looping serial bit streams, and therefore to avoid interrupting test patterns.
With the foregoing background in mind, it is an object of the invention to produce serial bit streams without unwanted timing gaps.
To achieve the foregoing object, as well as other objectives and advantages, a circuit for generating one or more serial bit streams includes a memory coupled to a reformatter, which is in turn coupled to a serializer for converting parallel data to serial data. The memory includes a plurality of words having a known bit width (e.g., 32 bits) for storing one or more serial bit. The length of each serial bit stream may not be an integer multiple of the memory""s bit width. Consequently, one of the words storing each serial bit stream may contain a gap. The reformatter eliminates each such gap by combining bits from the word containing the gap (generally the word encoding the end of a current loop) with bits from the next word (generally the word encoding the beginning of a next loop) to provide a completely filled word to the serializer. As operation proceeds, the reformatter continues to combine bits from successive words to ensure that completely filled words are produced. Gaps that formerly appeared when producing serial bit streams are thereby eliminated.